Converting information in the form of analog signals to equivalent information in digital form is historic and ubiquitous in the microelectronics industry. This is because a great deal of the information produced by the physical world is analog in nature, e.g., audio signals, video signals, magnetic and electric fields, etc. As the ability to process information in digital form increases exponentially with the sophistication and scaling of digital integrated circuits, there is an ever increasing desire to convert analog signals to digital form to take advantage of these increased digital processing capabilities.
There are several approaches to the task of converting analog signals to digital form. These include various architectures or algorithms that can be implemented using analog and digital circuit designs. These architectures include flash analog-to-digital converters (ADCs), delta-sigma ADCs, pipelined ADCs, and several others. Two notable specifications of interest in an ADC are the sampling rate and the nominal resolution. The sampling rate is the rate in samples per second (S/s) at which the analog input is converted to a digital output. The nominal resolution is the number of bits in the digital output and is related to the accuracy with which the digital output represents the analog input. For example, in a one-bit ADC, the only property of the input that can be expressed in the output is whether or not it is above or below some level; in a two bit converter the input can be expressed as being in one of four regions, etc. As the number of bits of precision is increased, the accuracy with which the digital output approximates the true analog input improves but the error never goes to zero. This so-called quantization error is an inherent impairment of analog-to-digital converters.
One approach to analog-to-digital conversion is called successive approximation. In this approach, as with all ADCs, the analog input is constrained to fall within some predetermined range called the full-scale range. In a successive approximation converter, a digital-to-analog converter (DAC) whose output is constrained to nominally the same full-scale range is present. In a first processing step, the analog signal is sampled and held for subsequent conversion steps. In a second conversion step, a comparator circuit compares the sampled analog input to the DAC output when the DAC input is set to exactly one-half of its full-scale digital range. By this method, the analog input is determined to be in either the bottom half of the full-scale range (e.g., when the comparator output reads binary zero) or in the top half of the range (e.g., when the comparator reads a binary one). The result of this decision is the most significant bit (MSB) of the ADC's digital output. In a third conversion step, the DAC input is re-set to a value halfway between its half full scale value and either the zero value or the maximum value depending on the result of the comparison in the second step. By this method, the analog input is determined to be in either the bottom half or the top half of the remaining possible range of values after the result of the comparison in the first step. In subsequent conversion steps, this process is repeated until all bits in the ADC digital output are decided.
The successive approximation converter provides analog simplicity and ease of implementation in digital-centric CMOS integrated circuit fabrication processes. Such a converter requires at least ‘N’ steps to complete its task, where ‘N’ is the number of bits in the digital output. Typically at least one additional step is added to allow for sampling and/or settling at the analog input. A number ‘m’ of additional steps may be added for other purposes, bringing the total number of steps to N+1+m. Each step in the conversion process is typically allotted a fixed time ‘T’ associated with the period of a clock available on the chip/system in which the ADC operates. As a result, the time required for each conversion is Tconv=(N+1+m)*T seconds where the converter sample rate is limited to 1/Tconv samples per second (S/s).
Another approach to analog-to-digital conversion is time interleaving. In this approach, a plurality of identical converter unit cells operate on an analog signal sampled at a multiple of the sample rate of each converter, where the multiple is equal to the number of converter unit cells in the plurality of converter unit cells. For an analog signal sampled at time interval T seconds, e.g., having a sample rate of 1/T samples/second (S/s), two converters each operating at a sample rate of ½T S/s can be used to digitize these samples at an aggregate rate of 1/T S/s. A first analog sample is sent to the first of the two converters at time zero and a second analog sample is sent to the second converter at time T. The first converter completes its task at time 2T, at which time a third analog sample is sent; the second converter completes its task at time 3T and a fourth analog sample is sent; and the process repeats. Similarly, three identical converters operating at a sample rate ⅓T can achieve the same result, and so on. Each additional cycle required by the individual converter can be accommodated at the same system sample rate by adding another converter to the plurality of converters in the time interleaved system. In this manner a plurality of N slow converters can be operated in such a way as to achieve an effective sample rate of N times the sample rate of the slow converters.
A notable characteristic of any ADC is its gain. Since the function of an ADC is to convert an analog input to digital codes at the output, the gain has the units of codes per unit of analog input, e.g. codes/volt. For example, an ADC having a gain of 1000 codes/volt increases its output digital code by 1 when the analog input value increased by 1 mV. More generally, the ADC analog input is typically taken as a ratio with respect to the full scale reference potential and the transfer function may also feature some offset, so the equation for the transfer function is given by Equation 1:Code_Out=2N*(Vin+Vos)/Vref+Center_Code  (1).
In Equation 1, Vin is the analog input to the ADC and Vref is the analog full-scale reference voltage. N is the number of bits of resolution in the ADC. Vos is any offset that may be present in the analog signal or offset introduced in the ADC itself. A quantity Center_Code, typically 2N−1, is added to avoid the need for a sign bit in the output when the analog input takes on both positive and negative values.
In a time-interleaved converter comprising a plurality of ADC units, each ADC unit ideally matches all of the others. Specifically, both the gain and the offset are the same for all ADC units in the time-interleaved block. This may not, however, be the case due to random variations in electrical parameters of the devices used to build the ADC units. For example, each unit may have a statistical offset that results from random mismatches in the components used to construct the comparator circuit, e.g., MOS (metal oxide semiconductor) or bipolar transistors primarily but also potentially various types of integrated passive components such as resistors and capacitors. Separate from (e.g., independent of) such offset, each ADC may additionally or alternatively have a gain error of some magnitude, resulting in a transfer function after offset cancellation given by Equation 2:Code_Out=Ax*2N*Vin/Vref+Center_Code  (2).
In Equation 2, the term ‘Ax’ is a gain error term statistically distributed around 1.00. Equivalently, errors resulting from non-idealities in Vref (e.g., noise, ohmic drops in distribution wires, etc.) between units in the ADC also can manifest as gain errors. Gain errors subsequently manifest as errors in the output of the ADC. For example, when a constant analog input is applied to two nominally identical ADC units, gain error associated with one or both of the units may cause the units to produce different digital results. These gain errors can be measured and quantified using traditional ADC characterization techniques including signal to noise ratio and signal to noise and distortion.
Additionally, offset cancellation techniques typically eliminate offset generated within a time-interleaved ADC but are incapable of eliminating offsets springing from other sources external to the ADC. Such sources can include the electronics driving the ADC and other elements upstream of the ADC.
An additional complication occurs when the time-interleaving of ADC unit cells have two levels (e.g., a two-level time-interleaved ADC). In a dual level time interleaved ADC, the ADC unit cells are themselves comprised of a plurality of sub-unit cells sampling at an even lower rate. For example, a two-level 32 GS/s ADC may comprise four 8 GS/s ADC blocks, each of which is in turn comprises sixteen 500 MS/s unit cells. The full-scale reference voltages may be generated at the level of the 8 GS/s blocks, but the underlying reference voltages from which these full-scale references are generated must be connected to all four of the 8 GS/s blocks without loss of accuracy. Typically this level of accuracy is impossible, resulting in the need for a gain calibration.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.